Saturday, July 03, 2010

A poor/slow man's FPGA? It might be closer than you think.

Got a paperback copy of "Designing Logic Systems Using State Machines" today off Amazon... the bit about ROM-based logic (a precursor to CPLD's?) got me thinking that one could translate a logic circuit design into assembly code for a microcontroller. It could use a mixture of ROM and direct assembly operations, tuning it according to the target CPU in question.

Such a program would be slow by logic standards (at least if you wanted more than the simplest functions!) but with non-pin-related interrupts off and non-branching code, the timing could be completely predictable.

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